例句與造句

1. The part of execution in which an operand or instruction is read from main stora ge and written into a control unit or arithmetic unit register
   執(zhí)行過程中的一個階段所需的時間，在此期間，計算機從主存儲器中取出指令或操作數(shù)，并將其存入控制器或運算器的寄存器中。
2. In modern vlsi technology , hundreds of thousands of arithmetic units fit on a 1cm 2 chip . the challenge is supplying them with instructions and data . stream architecture is able to solve the problem well
   在摩爾定律作用下，在單芯片上可集成的晶體管數(shù)快速增長，單芯片擁有成百上千的運算單元不再是問題，關鍵是如何給如此多的alu提供足夠的指令和數(shù)據(jù)。
3. 3 - d graphics on mobile phones is quite similar to 3 - d graphics on pc in years past . there is no hardware acceleration , and processor speeds are quite low , and there also is the lack of floating point arithmetic unit in mobile phones
   因此論文從通用的部分開始論述,然后明了移動平臺的特征,并試圖解釋三維引擎的一般原理和設計一個具有粗適性的基于游戲的三維圖形引擎。
4. 2 montoye r k , hokenek e , runyon s l . design of the ibm risc system 6000 floating - point execution unit . ibm journal of research and development , 1990 , 34 : 59 - 71 . 3 oberman s . floating - point arithmetic unit including an efficient close data path
   我們采用90納米cmos標準單元工藝以及synopsys自動布局布線流程進行實驗，實驗結果表明該算法在高性能雙通路結構的浮點加減運算中引入后，可以使得近路徑的運算延遲整體降低10 . 2 % ，且算法本身沒有造成新的關鍵路徑。
5. So , we must design multimedia application - oriented computer architecture to fit the data processing demand of video compressing programs , we analyzed the parallelism of two representative video compressing programs - opendivx and tml9 , and drew a conclusion that it is effective to run video compressing application programs on the processor which uses parallel arithmetic units
   相對于視頻壓縮應用而言，普通計算機的處理能力大大落后于處理需求。因此，對于多媒體應用，必須采用并行的方法來解決，但是不能簡單地使用普通并行機，必須針對這部分應用的特點，采用并行的思想來設計面向多媒體應用的計算機體系結構。
6. It's difficult to find arithmetic unit in a sentence. 用arithmetic unit造句挺難的
7. With turning the scale of asic ( appl ication specified integrated circuits ) to s0c ( system on chip ) , which conunon1y is composed of mcu , specified function ip cores , memory , periphery interface etc , the ip reuse techno1ogy is very important in s0c design flow , which can realize the constructions of different levels components . the approach of configurable system , method and design f1ow for udsm ( u1tra deep sub micron ) asic , logic system design using hdl 1anguage , coding style , static and dynamic verification strategy are a1so presented in chapter 2 . in chapter 3 we study the vlsi - - dsp architecture design , dense computation and high speed high performance digital signal processing unit structure , which includes high speed mac components and distributed arithmetic unit
   在工程設計方法及結構化設計和高層次綜合的研究中，介紹了在深亞微米工藝條件使用的方法和asic設計流程，討論了高層次綜合的核心如何從描述推出電路構成的設計思路，針對不同目標的設計技巧討論了采用hdl語言進行邏輯系統(tǒng)設計的方法，給出了用vhdl語言進行代碼設計時的規(guī)范和風格，在面向soc的驗證策略討論了動態(tài)和靜態(tài)的驗證技術，提出了進行單獨模塊驗證、芯片的全功能驗證和系統(tǒng)軟硬件協(xié)同驗證的整體策略。
8. After that , it gives the measures of designing dsp ' s assembler as a part of the dsp ' s software development environment together with the c - compiler . moreover , this paper explores the method of design the floating - point arithmetic unit . referring to the ieee754 - 1985 standard for binary floating - point arithmetic , the algorithm and the behavior description of floating - point adder and multiplier is given , and the simulation and verification is shown at the end of this paper
   此外，本文還對處理器的浮點運算單元設計做了初步的研究，以ansi ieee - 754浮點數(shù)二進制標準為參考，借鑒了經典的定點加法器和乘法器的設計，嘗試性的給出了浮點加法單元和乘法單元的實現(xiàn)模型和行為級上的硬件描述，并對其進行仿真和驗證。